1. Field of the Invention
The present invention relates to a semiconductor memory device having a replica circuit for controlling the sense timing of a sense amplifier.
2. Description of the Related Art
An example of a conventional semiconductor memory device having a replica circuit will be described.
In the replica circuit, a dummy word line connected to a dummy row decoder runs through dummy cells arrayed in the column direction and turns back. The dummy word line is then connected to dummy cells arrayed in the row direction through a dummy bit line and further connected to a local sense activation circuit through, e.g., an inverter. The turnback is done in a distance half an actual word line (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-56682).
The dummy word line reflects the actual word line length up to the farthest point. Hence, the dummy bit line reproduces the farthest bit line. The replica circuit determines the sense start timing, and generates a sense start signal (sense activation signal) and notifies the sense amplifier of the cell array of the start of sensing. For this reason, “dummy word line delay+dummy bit line delay+inverter delay+interconnect delay up to sense amplifier” is necessary until a signal is transmitted to the farthest sense amplifier.
Conventionally, since the word lines are made of polysilicon and the necessary memory capacity is small, the interconnect delay up to the sense amplifier is so small as to be insignificant as compared to the dummy word line delay or dummy bit line delay. However, with the advance of process, the required memory capacity increases, and the material of word lines changes from polysilicon to a metal. Thus, although the dummy word line delay decreases, the interconnect delay up to the sense amplifier becomes equal to or more than the word line delay and cannot be neglected any more.
Additionally, after word line activation in the cell array, the potential difference between the pair of bit lines closest to the row decoder is different from that in the pair of bit lines farthest from the row decoder because of the interconnect delay up to the farthest sense amplifier. For example, assume that 512 cell arrays are arranged, and the farthest sense amplifier should start sensing when the potential difference between the pair of bit lines is 100 mV. In this case, however, the potential difference between the pair of bit lines reaches 130 mV because of the interconnect delay up to the sense amplifier.
FIG. 7 shows an example of the potential difference between the pair of bit lines in this operation. As shown in FIG. 7, when a potential difference ΔLBL in a pair of bit lines is 100 mV, the sense start signal is activated. However, the farthest pair of bit lines starts sensing with a considerably large potential difference because of the interconnect delay of the sense start signal. Although the large potential difference between the pair of bit lines is welcome from the viewpoint of a larger sense margin, it also limits the operation speed. For a faster operation, it is necessary to decrease the above-described interconnect delay up to the extra sense amplifier.